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Design of a multiport memory controller

This report describes the design of a multi-port DDR2 memory controller using the
high-level hardware description language Bluespec SystemVerilog (BSV). The purpose
of the implementation of the design was the evaluation of Bluespec System-
Verilog and the Bluespec compiler and to compare the Bluespec design flow with a
traditional design flow using register transfer level Verilog or VHDL.

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