Training introduction to Universal Verification Methodology (UVM)
This 4 day course is for engineers interested in developing SystemVerilog verification environments using the latest Universal Verification Methodology (UVM).
Students will first learn:
- Basic testbench structure
- How to model communication at the transaction level (TLM)
- How to write analysis components such as Scoreboards and Coverage Collectors
- Strategies for connecting to RTL designs
After mastering the basics, students will learn best-practice techniques to maximize the reusability of their test environments. Topics include:
- Using the UVM factory
- Managing complexity using hierarchy and factory overrides
- Making reusable testbenches
- Developing test cases using UVM sequences
- Using UVM Registers
- Introduction to UVM
- Transaction-level Communication
- TLM Interfaces, Channels, Port & Exports
- Basic Testbench Structure
- Start and end of simulation
- Dynamic Construction - Introduction to the UVM Class Factory
- Connecting to the DUT
- Generating Reports and Messaging
- Modeling Transactions
- UVM Analysis components
- Scoreboards, coverage collectors, predictors
- UVM Components and Hierarchy
- Hierarchical API
- Creating a Configurable Test Environment
- Factory Overrides
- Resources, configurations
- Stimulus generation
- Scenarios (testing patterns)
- UVM registers
- Register model development
- Register model integration
- Register model usage
A good portion of class time will be spent applying principles learned in lecture to hands-on labs
Verification & Design engineers.
Ir. Gert-Jan Tromp.
Training center van Dizain-Sync b.v., Borne.
On-site courses on request.