This 3 day training is meant as an introduction into VHDL. VHDL, as it seems, only knows advantages, but the complexity of VHDL can be very frustrating for new users: why is my description doing different things than I intended?
Mr. B. Molenkamp will make sure you will have enough experience to understand most VHDL descriptions and to describe small problems in VHDL yourself. This training is meant for designers of digital systems.
During the training theory and practice will be interchangeable. Besides VHDL aspects (like simulation model, entity, architecture, package, configuration) also design of digital systems in VHDL and synthesis of VHDL will come up for discussion. The training is aimed at the IEEE standard, not at a specific VHDL tool. During practice you will work with another participant. During practice different tools can be used. If a training is held on site, tools will be used which the trainee will use after the training.
The training has been given by B. Molenkamp, teacher at the faculty Electrical engineering, Mathematics and Informatics of the Universiteit Twente. He is a VHDL trainer at Dizain-Sync B.V. since 1989.
The training will take 3 days.
A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.
This 3 day course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. We also cover how to construct testbenches for unit level verification of your RTL code.
This course continuously mixes lecture and exercise. There is a simulation exercise for most topics providing a very hands-on experience. Synthesizable constructs are clearly identified and appropriate synthesis coding techniques discussed.
We can offer this class with most popular simulators.
• Verilog modeling
• Using your Simulator
• Verilog basics
• Procedural assignments
• Design a sequential pipe
• Synthesizing your design
• Programming statements
• Sensitivity lists
• Continuous assignments
• Timing accuracy
• Verification using Verilog
• Synthesis issues
• Finite State machines (exercise)
A digital design background and preferably some programming experience in C or another language.
The Application Support Engineer is responsible for providing high-quality technical support for the EDA design flow of the customer. The Application Support Engineer is responsible for solving issues in the tooling so that the customer can ...
The Application Support Engineer is responsible for providing high-quality technical support for the EDA design flow of the customer. The Support Engineer is responsible for solving issues in the tooling so that the customer can continue des...