Dizain-Sync B.V.
Oostermaat 2
7623 CS Borne, the Netherlands

+31 (0)74 2650 050
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Professional VHDL


This 3 day training is meant as an introduction into VHDL. VHDL, as it seems, only knows advantages, but the complexity of VHDL can be very frustrating for new users: why is my description doing different things than I intended? 

Mr. B. Molenkamp will make sure you will have enough experience to understand most VHDL descriptions  and to describe small problems in VHDL yourself. This training is meant for designers of digital systems.


Training
During the training theory and practice will be interchangeable. Besides VHDL aspects (like simulation model, entity, architecture, package, configuration) also design of digital systems in VHDL and synthesis of VHDL will come up for discussion. The training is aimed at the IEEE standard, not at a specific VHDL tool. During practice you will work with another participant. During practice different tools can be used. If a training is held on site, tools will be used which the trainee will use after the training.

Trainer
The training has been given by B. Molenkamp, teacher at the faculty Electrical engineering, Mathematics and Informatics of the Universiteit Twente. He is a VHDL trainer at Dizain-Sync B.V. since 1989.

Duration
The training will take 3 days. 

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Advanced VHDL


The advanced VHDL training is meant for designers who work some time with VHDL (designers, but also for engineers who describe test environments). During the training, where theory and practice will vary, the base knowledge will be refreshed and afterwards the less known aspects of VHDL will be considered. Trainees will work on their own case. For this case, alternative descriptions will be discussed about the pro's and con's for simulation and synthesis.
 
Subjects
  • Intensification in VHDL (simulation and synthesis), a.o
    • Simulation model
    • Waveforms, transactions, guarded signals (bus, register), (disconnection of) drivers
    • Delay mechanisms
    • File IO (formatted and text)
    • Overloading, qualification
    • Protected types, shared variable
    • Resolution function
    • Impure/pure functions
    • Implicit signals
  • Introduction Verilog. Often a VHDL user will get in contact with Verilog, e.g. when a synthesis tool generates Verilog output. Also co-simulation of VHDL and Verilog occurs.
  • VITAL (VHDL Initiative Towards ASIC Libraries) enables post simulations with a VHDL simulator, with the 'real' delays of hardware. This enables automatic control for timing constraints. Although it was intentionally meant for ASIC's, it is now a commodity for FPGA's.
  • PSL (Property Specification Language). With the increasing complexity of designs, the need for different verification methods increases. For the hardware description languages, there has been chosen for PSL; an IEEE standard. Nowadays, a lot of VHDL simulators support (embedded) PSL.
  • Choices have been made to give the training to a relatively small group of students. This give the ability to change the training on the fly. For instance, some more attention can be given to :
    • VHDL-AMS (Analog Mixed Signal). A superset of VHD, which enables the creation of analog models. This has been used in the automotive industry!
    • State machines (part of Fundamentals & Synthesis training).
    • Numeric_std (part of Fundamentals & Synthesis training)

Trainer
The training has been given by B. Molenkamp, teacher of the faculty Elektrotechniek, Mathematics and Informatica of the Universiteit Twente. He is a VHDL trainer at Dizain-Sync B.V. since 1989.

Target group
The training is very suitable for those who have worked some time with VHDL (as a designer, but also for test engineers who describe test environments). The training is less suitable for the beginning VHDL user. For them, the training Professional VHDL would be better.

Duration
The training will take 2 days. 
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Introduction to Verilog


A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

This 3 day course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. We also cover how to construct testbenches for unit level verification of your RTL code.
This course continuously mixes lecture and exercise. There is a simulation exercise for most topics providing a very hands-on experience. Synthesizable constructs are clearly identified and appropriate synthesis coding techniques discussed.

We can offer this class with most popular simulators.

Syllabus

• Verilog modeling
• Using your Simulator
• Verilog basics
• Procedural assignments
• Design a sequential pipe
• Synthesizing your design
• Operators
• Programming statements
• Sensitivity lists
• Continuous assignments
• Primitives
• Tasks
• Functions
• Timing accuracy
• Verification using Verilog
• Bi-directionals
• Synthesis issues
• Finite State machines (exercise)

Prerequisites
A digital design background and preferably some programming experience in C or another language. 

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